Publications

2024

• Invited: Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants. Vidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, and Sachin S. Sapatnekar. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’24). Oct 2024.
  
• OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks. Utsav Sharma*, Bing-Yue Wu*, Sai Rahul Dhanvi Kankipati, Vidya A. Chhabria, and Austin Rovinski. In 2024 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD ’24). Sep 2024.
  
• EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD. Bing-Yue Wu*, Utsav Sharma*, Sai Rahul Dhanvi Kankipati, Ajay Yadav, Bintu Kappil George, Sai Ritish Guntupalli, Austin Rovinski, Vidya A. Chhabria. In The First IEEE International Workshop on LLM-Aided Design (LAD'24). Jun 2024.
  

2022

• The Case for Using Guix to Enable Reproducible RISC-V Software & Hardware. Christopher Batten, Pjotr Prins, Efraim Flashner, Arun Isaac, Jan van Nieuwenhuizen, Ekaitz Zarraga, Tuan Ta, Austin Rovinski, Erik Garrison. In Sixth Workshop on Computer Architecture Research with RISC-V (CARRV 2022). Jun 2022.
  
• Towards Free, Open, and Ubiquitous Hardware Design. Austin Rovinski. In University of Michigan Deep Blue (Doctoral Dissertation). May 2022.
  

2020

• Bridging Academic Open-Source EDA to Real-World Usability: Invited Paper. Austin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, Mehdi Saligane. In International Conference On Computer Aided Design (ICCAD). Nov 2020.
  [Paper] [BibTeX]
• Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices. Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Yuhan Chen, Ronald G. Dreslinski, Trevor Mudge. In International Conference on Supercomputing (ICS). Jun 2020.
  [Paper]
• A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald G. Dreslinski. In IEEE Journal of Solid-State Circuits (JSSC). Jan 2020.
  [Paper] [BibTeX]

2019

• Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL. Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski. In IEEE Solid-State Circuits Letters (SSC-L). Nov 2019.
  [Paper]
• A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS. Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski. In 2019 Symposium on VLSI Technology (VLSI). Jun 2019.
  [Paper]
• A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. Subhankar Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald G. Dreslinski. In 2019 Symposium on VLSI Technology (VLSI). Jun 2019.
  [Paper]
• OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain. Tutu Ajayi, David Blaauw, Tuck-Boon Chan, Chung-Kuan Cheng, Vidya A. Chhabria, David K. Choo, Matteo Coltella, Sorin Dobre, Ronald G. Dreslinski, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jiajia Li, Zhaoxin Liang, Uday Mallappa, Paul Penzes, Geraldo Pradipta, Sherief Reda, Austin Rovinski, Kambiz Samadi, Sachin S. Sapatnekar, Lawrence Saul, Carl Sechen, Vaishnav Srinivas, William Swartz, Dennis Sylvester, David Urquhart, Lutong Wang, Mingyu Woo, and Bangqi Xu. In Government Microcircuit Applications & Critical Technology Conference (GOMACTech). Mar 2019.
  [Paper]

2018

• The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawai, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor. In IEEE Micro. Apr 2018.
  [Paper]

2017

• Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm. Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, and Zhiru Zhang. In First Workshop on Computer Architecture Research with RISC-V (CARRV 2017). Oct 2017.
  [Paper] [BibTeX]
• Celerity: An Open Source RISC-V Tiered Accelerator Fabric. Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, and Zhiru Zhang. In Symposium on High Performance Chips (Hot Chips 29). Aug 2017.
  [Slides] [BibTeX]
• A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic. Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski. In Proceedings of the 2017 International Symposium on Low Power Electronics and Design (ISLPED). Jul 2017.
  [Paper] [BibTeX]
• Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge. Yiping Kang, Johann Hauswald, Cao Gao, Austin Rovinski, Trevor Mudge, Jason Mars, and Lingjia Tang. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Apr 2017.
  [Paper] [BibTeX]

2016

• Sirius Implications for Future Warehouse Scale Computers. Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars. In IEEE Micro (Top Picks). May 2016.
  [Paper] [BibTeX]
• Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant. Johann Hauswald, Michael A Laurenzano, Yunqi Zhang, Hailong Yang, Yiping Kang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, and Jason Mars. In ACM Transactions on Computer Systems (TOCS). Apr 2016.
  [Paper] [BibTeX]

2015

• Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers. Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor Mudge, Vinicius Petrucci, Lingjia Tang, and Jason Mars. In Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Mar 2015.
  [Paper] [BibTeX]