2022
- The Case for Using Guix to Enable Reproducible RISC-V Software & Hardware.
- Towards Free, Open, and Ubiquitous Hardware Design.
2020
- Bridging Academic Open-Source EDA to Real-World Usability: Invited Paper.
[Paper] [BibTeX]- Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices.
[Paper]- A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
[Paper] [BibTeX]
2019
- Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL.
[Paper]- A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS.
[Paper]- A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
[Paper]- OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain.
[Paper]
2018
- The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
[Paper]
2017
- Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm.
[Paper] [BibTeX]- Celerity: An Open Source RISC-V Tiered Accelerator Fabric.
[Slides] [BibTeX]- A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic.
[Paper] [BibTeX]- Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge.
[Paper] [BibTeX]
2016
- Sirius Implications for Future Warehouse Scale Computers.
[Paper] [BibTeX]- Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant.
[Paper] [BibTeX]
2015
- Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers.
[Paper] [BibTeX]
